A test apparatus for testing switching speed of a circuit, which includes a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, is provided, wherein the post-stage logic element includes the post-stage FET, a gate terminal of which the output signal is input to, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage, and the test apparatus includes a threshold voltage setting unit for setting a threshold voltage of a post-stage field effect transistor (FET) to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit; a delay time measuring unit for measuring a delay time of the circuit to which the threshold voltage different from that in the normal operation is set; and an error detecting unit for detecting an error in switching speed of the circuit based on the delay time.
A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.
