Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong "on" state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a V.sub.DD ESD protection element connected between an I/O pad and a V.sub.DD line, a ground voltage (V.sub.SS) ESD protection element connected between the I/O pad and a V.sub.SS line, and a power clamp element connected between the V.sub.DD line and the V.sub.SS line, and wherein the V.sub.DD ESD protection element, the power clamp element, and the V.sub.SS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

An ESD protection circuit includes a detection circuit for detecting an ESD current and a bypass circuit for bypassing the ESD. The detection circuit and bypass circuit are connected to a first pad and a second pad. The bypass circuit is connected to an output terminal of the detection circuit. The bypass circuit comprises a MOS transistor, a first bipolar transistor and a second bipolar transistor. The drain of the MOS transistor, the collectors of the first bipolar transistor and the collector of the second bipolar transistor are connected to the first pad. The source and the substrate of the MOS transistor and the emitter of the second bipolar transistor are connected to the second pad. The base of the first bipolar transistor is connected to the gate of the MOS transistor and the emitter of the first bipolar transistor is connected to the base of the second bipolar transistor.

A circuit arrangement includes an RC element connected between a first supply potential line and a second supply potential line. The RC element includes a first resistor and a first capacitor. The circuit arrangement also includes a plurality of inverters connected in series and having junction points between the inverters in the plurality of inverters. An input of the plurality of inverters is connected to a point between the first resistor and the first capacitor. The circuit arrangement also includes a protection transistor and a plurality of resistors.