A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for each ASIC. The data object includes both control and data portions. A TC scheduling circuit coordinates transfer of data objecst to and from a TC data object memory that is local or external. The TC data object memory is shared in common with all the ASIC blocks so that computation results from each ASIC TC signal processing circuit can be passed between other ASICs to form a logical pipeline. The data objects output from the TC subsystem are used by other processing subsystems in an xDSL communications system, including a software based ATM TC subsystem, and a physical medium dependent subsystem. In addition, the architecture of the TC subsystem is configured so that it can be shared by multiple ports in an xDSL system. The individual ASICs are also adapted to be multi-tasking to further reduce hardware requirements.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional No. 60/185,964 filed Mar. 1, 2000.
The present application is further related to the following applications, all of which are being filed contemporaneously herewith, and all of which are hereby incorporated by reference.
Scaleable Architecture for Multiple-Port, System-on-Chip ADSL Communications Systems; U.S. application Ser. No. 09/797,633, filed Mar. 1, 2001;
System and Method for Internal Operation of Multiple-Port xDSL Communications Systems; U.S. application Ser. No. 09/797,789, Filed Mar. 1, 2001;
xDSL Communications Systems Using Shared/Multi-function Task Blocks;- U.S. application Ser. No. 09/797,778, filed Mar. 1, 2001;
Mixed Hardware/Software Architecture and Method for Processing xDSL Communications; U.S. application Ser. No. 09/797,793 filed Mar. 1, 2001, now U.S. Pat. No. 6,839,889.
xDSL Symbol Processor & Method of Operating Same; U.S. application Ser. No. 09/797,782, filed Mar. 1, 2001;
Logical Pipeline for Data Communications System; U.S. application Ser. No. 09/798,054, Filed Mar. 1, 2001, now U.S. Pat. No. 6,839,830.
xDSL Function ASIC Processor & Method of Operation; U.S. application Ser. No. 09/798,133, filed Mar. 1, 2001;
Data Object Architecture and Method for xDSL ASIC Processor; U.S. application Ser. No. 09/797,755, filed Mar. 1, 2001;
Programmable Task Scheduler for Use with Multiport xDSL Processing System;- U.S. application Ser. No. 09/797,648, filed Mar. 1, 2001;
Physical Medium Dependent Sub-System with Shared Resources for Multiport xDSL System; U.S. application Ser. No. 09/798,113, filed Mar. 1, 2001.
