A priority-based arbiter for arbitrating access to a shared resource by at least two competing devices. The priority-based arbiter intercepts access request signals generated by at least one of the competing devices and generates a respective modified bus request signal. The respective modified bus request signal may be delayed for a predetermined period of time associated with the state (e.g., idle, low priority context, and high priority context) of at least one of the competing devices.
A priority determining unit determines a priority of a status of a device connected to a second bus that is connected, via a bridge, to a first bus to which a central processing unit and a storage unit are connected. A bus-status determining unit determines a use status of the second bus. A status writing unit writes the status to the storage unit based on a result of determination by the priority determining unit and a result of determination by the bus-status determining unit.
A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers with higher priority data transfers. All devices on the bus are configured with a latency timer setting of zero or a non-zero value which guarantees required data transfer latencies are met which means that any device will terminate bus-master transfers quickly upon the bus grant signal being de-asserted. To ensure a transfer completes, bus grant for the priority transfer is asserted until entire data transfer completion is imminent, enabling transfers, such as high priority transfers, to complete uninterrupted.
