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Two dimensional data eye centering for source synchronous data transfers
   
Document Number
US Patent 7036053
Issued Date
April 25, 2006
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Abstract
A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.
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Number of Claims:
36
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Owner
Intel Corporation (Santa Clara, CA)
Published
April 25, 2006
Application Number
10/324,864
Filed
December 19, 2002
US Classification
714/709   714/719 714/721 714/744
Int'l Classification
G01R   31/3183   (20060101)  
USPTO Field of Search
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