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Circuit arrangement for controlling power semiconductor transistors
   
Document Number
US Patent 7038500
Issued Date
May 2, 2006
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Abstract
A current regulated circuit arrangement for controlling a power semiconductor transistor, as example a MOSFET or IGBT power transistor, that includes at least two mirror-symmetrically arranged regulated power sources and an output voltage regulator. A first regulated power source is fed from an unregulated power source and controls the gate of the power transistor such that the power transistor is switched into the conductive state. A second regulated power source is fed from an unregulated power source and controls the gate of the power transistor such that the power transistor is switched into the non-conductive state. A voltage regulator or limiter limits the current at the gate of the power transistor to a operably suitable maximum value.
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Number of Claims:
25
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Owner
Published
May 2, 2006
Application Number
10/638,664
Filed
August 11, 2003
US Classification
327/108   327/427
Int'l Classification
H03B   1/00   (20060101)  
Examiner
Priority Data
Aug 09, 2002 [DE] 102 36 532
USPTO Field of Search
327/108   327/109   327/110   327/111   327/112   327/427   327/530   327/538   327/309   327/312   327/313   327/314   327/315   327/316   327/323   327/324   327/327   327/328  
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