In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.
This application is a Continuation of application Ser. No. 09/788,899 filed on Feb. 20, 2001, now U.S. Pat. No. 6,480,919, which is a Continuation of application Ser. No. 09/152,597 filed on Sep. 14, 1998, now U.S. Pat. No. 6,275,893.
A method and system for providing a common operating system feature set for supporting a variety of operating system configurations is described. The common operating system feature set is organized to provide a minimal memory footprint applicable to a number of devices and methods of deployment. The common operating system includes dependencies among operating system components that provide a selection of integrated components that are validated for reliability. The common operating system includes an application program interface set that provides functionality for a variety of operating system scenarios.
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.
