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Nonvolatile semiconductor memory device
   
Document Number
US Patent 7045866
Issued Date
May 16, 2006
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Abstract
This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data "1" or "0" in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.
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Number of Claims:
8
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Owner
Published
May 16, 2006
Application Number
10/981,753
Filed
November 5, 2004
US Classification
257/390   257/391
Int'l Classification
H01L   29/76   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Nov 05, 2003 [JP] 2003-375382
USPTO Field of Search
257/390   257/391   257/208   257/209   257/202   257/204   257/205   257/210   257/211  
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