A power management system and circuit comprising instructions stored in computer memory for the prevention of simultaneous coupling of more than one power source to a device under test (DUT). Instructions stored in memory prevent the simultaneous application of power to the DUT from both the in circuit emulator power grid and an external power source. External power applied to the DUT results in at least one activity signal detected by the computer. If no activity signal appears, a fault condition in the DUT is interpreted. If an activity signal is detected, testing continues under control of Debug Software.
