A new nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element which is written using inductive write lines. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, and a second ferromagnetic layer with a non-changeable magnetization state. A current of spin polarized electrons has a magnitude which can be varied so that a data value can be stored in the memory element by varying a relative orientation of the two ferromagnetic layers using a magnetic field imposed by the inductive write lines.
RELATED APPLICATION DATA
The present invention claims priority to and is a continuation of application Ser. No. 10/776,987 filed Feb. 10, 2004 entitled "Hybrid Semiconductor--Magnetic Spin Based Memory," now U.S. Pat. No. 6,804,146 which in turn is a continuation of application Ser. No. 10/100,210 filed Mar. 18, 2002 entitled "Magnetoelectronic Memory Element With Inductively Coupled Write Wires," now U.S. Pat. No. 6,741,494. Application Ser. No. 10/100,210 is a continuation of an application Ser. No. 09/532,706 filed Mar. 22, 2000 titled "Magnetoelectronic Memory Element With Isolation Element" (now U.S. Pat. No. 6,388,916). The latter application Ser. No. 09/532,706 is in turn a divisional application of Ser. No. 08/806,028 filed Feb. 24, 1997 entitled "Hybrid Hall Effect Memory Device & Method of Operation," now U.S. Pat. No. 6,064,083. Ser. No. 08/806,028 is a continuation-in-part of Ser. No. 08/643,805, filed May 6, 1996 titled "Hybrid Hall Effect Device and Method of Operation," (now U.S. Pat. No. 5,652,445), which in turn is a continuation-in-part of an application Ser. No. 08/493,815, filed Jun. 22, 1995 titled "Magnetic Spin Transistor Hybrid Circuit Element," (now U.S. Pat. No. 5,565,695); and said Ser. No. 08/806,028 is also a continuation-in-part of an application Ser. No. 08/425,884, filed Apr. 21, 1995 titled "Magnetic Spin Transistor, Logic Gate & Method of Operation," (now U.S. Pat. No. 5,629,549); and an application Ser. No. 08/643,804 filed May 6, 1996 titled "Magnetic Spin Injected Field Effect Transistor and Method of Operation," (now U.S. Pat. No. 5,654,566).
The above applications and materials are expressly incorporated by reference herein.
