An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.
COPYRIGHT
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reporduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
PRIORITY
This application claims priority to U.S. provisional patent application Ser. No. 60/189,522, filed Mar. 15, 2000 and entitled "Method and Apparatus for Processor Code Optimization Using Code Compression."
RELATED APPLICATIONS
This application is related to pending U.S. patent application Ser. No. 09/418,663, filed Oct. 14, 1999 entitled "Method and Apparatus for Managing the Configuration and Functionality of a Semi-Conductor Design", which claims priority benefit of U.S. provisional patent application Ser. No. 60/104,271, filed Oct. 14, 1998, of the same title.
A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are received for a set of constraints for generating test simulation vectors for branch conditional instructions. Current resource values for predicting a branch for a branch conditional instruction are read. A branch operand field is generated to include a set of valid values using the current resource values and based upon said user selected constraints. The branch operand field defines conditions under which a branch is taken.
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.
Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value. Local sequential correlation compression such as PPM is then performed.
A nonvolatile memory stores encrypted data, which is obtained by linking and encrypting program data, in which combined data is compressed, and first information data indicating the number of programs contained in the combined data, and second information data indicating the size of each program. A CPU reads the encrypted data from the nonvolatile memory and decrypts the read encrypted data to restore the program data, the first information data and the second information data, after which the program data is decompressed to restore the combined data that is then stored in RAM. The CPU also creates a program management table for managing the respective programs based on the first and second information data, and stores the program management table in the RAM. The present invention is applicable to microcomputers.
Compression and decompression of data such as a sequential list of executable instructions (e.g., program binaries) by uniformly applying a predictive model generated from one segment of the executable list as a common predictive starting point for the other segments of the executable list. This permits random access and decompression of any segment of the executable list once a first segment (or another reference segment) of the executable list has been decompressed. This means that when executing an executable list (e.g., an executable file), a particular segment(s) of the executable list may not need to be accessed and decompressed at all if there are no instructions in that particular segment(s) that are executed.
