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Method of dicing a semiconductor wafer that substantially reduces the width of the saw street
   
Document Number
US Patent 7052977
Issued Date
May 30, 2006
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Abstract
A semiconductor wafer is diced utilizing a method that etches down to the top surface of the semiconductor wafer a number of times, such as during and following the formation of the metal interconnect structure, and then thins the semiconductor wafer from the back side until the semiconductor wafer singulates.
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Number of Claims:
19
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Published
May 30, 2006
Application Number
10/885,342
Filed
July 6, 2004
US Classification
438/460   257/E21.237 257/E21.599 438/703 438/736
Int'l Classification
H01L   21/46   (20060101)  
Attorney/Law Firm
USPTO Field of Search
438/460   438/689  
Related Patents
7482251 - Etch before grind for semiconductor die singulation - Owned by Impinj, Inc. (Seattle, WA)

Methods are provided, and devices made by such methods. One of the methods includes procuring a semiconductor wafer, processing the wafer to form a plurality of circuits on a top side, forming trenches on the top side between the adjacent circuits, forming a trench passivation layer on side walls of the trenches, forming conductive bumps on the top side of the wafer; and removing material from the bottom side to thin the wafer, and eventually separate the wafer along the trenches into dies, where each die includes only one of the circuits.

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