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Undershoot eliminator circuit and method for synchronous rectified DC-DC converters
   
Document Number
US Patent 7054168
Issued Date
May 30, 2006
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Abstract
An undershoot eliminator circuit is disclosed that avoids the occurrence of a negative undershoot that typically happens when an isolated DC-DC converter with a secondary side synchronous driver that is turned off. The undershoot eliminator circuit functions to discharge an energy storage element in an auxiliary supply on said secondary side of said converter. The circuit includes a clamp transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the transistor connected to said storage element, the source terminal of the transistor connecting to the output of the converter; means for trapping charge on the gate terminal of the clamp transistor while said converter is on; and means for coupling the voltage on the output of the converter to the gate terminal, such that, when said converter goes off and its output voltage begins to drop, the trapped charge causes the gate-to-source voltage of the clamp transistor to increase until the gate of the transistor is sufficiently saturated to cause it to turn on for a sufficient time to discharge the storage element. The undershoot eliminator circuit preferably employs a capacitor for trapping a charge on the gate terminal of the clamp transistor. The storage capacitor is quickly discharged to avoid a negative undershoot from occurring when the DC/DC power converter is turned off.
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Number of Claims:
11
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Owner
Astec International Limited (Hong Kong,unknown)
Published
May 30, 2006
Application Number
10/985,284
Filed
November 10, 2004
US Classification
363/21.06   363/127 363/21.14
Int'l Classification
H02M   3/335   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
363/21.06   363/21.14   363/53   363/56.11   363/127  
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Description
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