A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and generates a load-jump micro instruction, where the load-jump micro instruction directs load logic to retrieve an offset and directs the execution logic to generate a target address. The load logic is coupled to the paired operation translation logic and receives the load-jump micro instruction. The load logic retrieves the offset from memory, where the offset indicates a jump destination that is relative to an instruction address corresponding to the indirect near jump macro instruction. The execution logic is coupled to the load logic. The execution logic receives the offset, and employs the instruction address and the offset to generate the target address specifying the jump destination for the near jump operation.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application Ser. No. 60/345,448 filed on Oct. 23, 2001.
