Integrated gigabit ethernet PCI-X controller

What is claimed is:

1. A network controller, comprising: a. a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter having: (1) a clock signal input; (2) a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data; and (3) a predictive time base generator coupled with the clock signal input and the data delay element; and b. an alert supervisory controller coupled with the multiprotocol bus interface adapter, and adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus.

2. The network controller of claim 1, wherein the computer bus is adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof.

3. The network controller of claim 1, wherein the network controller is adapted to be a 10/100/1000BASE-T IEEE Std. 802.3-compliant network controller.

4. The network controller of claim 1, wherein the alert supervisory bus controller is adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP).

5. The network controller of claim 1, wherein: a. the multiprotocol bus interface adapter is adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof; b. the alert supervisory bus controller is adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP); and c. the network controller is adapted to be a 10/100/1000BASE-T IEEE Std. 802.3-compliant network controller.

6. The network controller of claim 5, further comprising: a. a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver coupled with the communication network; and b. a 10/100/1000BASE-T IEEE Std. 802.3-compliant media access controller (MAC) coupled with the transceiver.

7. The network controller of claim 6, further comprising a buffer memory coupled with the MAC.

8. The network controller of claim 7, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof.

9. The network controller of claim 7, further comprising a CPU used to transmit and a CPU used to receive coupled with the multiprotocol bus interface adapter and the alert supervisory bus controller.

10. The network controller of claim 9, wherein at least one of the multiprotocol computer bus interface adapter and the alert supervisory bus controller further comprises a Gigabit Media Independent Interface (GMII) interface, an 10-Gigabit Media Independent Interface (XGMII), a 10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface (XAUI), a Serial Gigabit Media Independent Interface (SGMII), a Reduced Gigabit Media Independent Interface (RGMII), a Reduced Ten Bit Interface (RTBI), a Ten-Bit Interface (TBI), a Serial Gigabit Media Independent Interface (SMII), and a Media Independent Interface (MII).

11. The network controller of claim 10, wherein the multiprotocol bus interface adapter interfaces one of an IEEE Std. 802.3-like protocol, a SONET/SDH-like protocol, a Fiber-Channel-like protocol, an SCSI-like protocol, and an InfiniBand-like protocol.

12. The network controller of claim 9, further comprising a single-chip VLSI device.

13. The network controller of claim 12, wherein the single-chip VLSI device is an 0.18 micron CMOS VLSI implementation.

14. The network controller of claim 1 wherein the time base generator includes a predictive synchronizer having a synchronizing feedback loop therein.

15. The network controller of claim 14 wherein the time base generator includes a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay, the replica delay element causing the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay.

16. A communication system, comprising: a. a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter having: (1) a clock signal input; (2) a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data; and (3) a predictive time base generator coupled with the clock signal input and the data delay element; b. an alert supervisory bus controller coupled with the multiprotocol bus interface adapter; adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus; and adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP); c. a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver coupled with the communication network; d. a 10/100/1000BASE-T IEEE Std. 802.3-compliant media access controller (MAC) coupled with the transceiver; e. a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and f. a CPU used to transmit and a CPU used to receive coupled with the multiprotocol bus interface adapter and the management bus controller to process data respectively transmitted to and received from the computer network; wherein at least one of the multiprotocol computer bus interface adapter and the alert supervisory bus controller further comprises a Gigabit Media Independent Interface (GMII) interface, an 10-Gigabit Media Independent Interface (XGMII), a 10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface (XAUI), a Serial Gigabit Media Independent Interface(SGMII), a Reduced Gigabit Media Independent Interface (RGMII), a Reduced Ten Bit Interface (RTBI), a Ten-Bit Interface (TBI), a Serial Gigabit Media Independent Interface (SGMII), and a Media Independent Interface (MII), and wherein the multiprotocol bus interface adapter interfaces one of an IEEE Std. 802.3-like protocol, a SONET/SDH-like protocol, a Fiber-Channel-like protocol, an SCSI-like protocol, and an InfiniBand-like protocol.

17. The communication system of claim 16, further comprising a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

18. The communication system of claim 17, wherein the single-chip VLSI device is implemented in one of a network interface card, and a LAN-on-Motherboard application.

19. A communication system as in claim 16 wherein the time base generator further includes a predictive synchronizer having a synchronizing feedback loop therein.

20. A communication system as in claim 19 wherein the time base generator further includes a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay, the replica delay element causing the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay and wherein the computer bus and the multiprotocol bus interface adapter are adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates to computer bus interfaces, particularly to high-performance, high-bandwidth computer bus interfaces, and more particularly to a computer bus interface adapter providing integrated alerting and management functions, and having a predictive time base generator therein.

BACKGROUND OF THE INVENTION

Modern communications networks are demanding heterogeneous environments having associated complex communication, management, and support requirements. Some components may act as servers under some circumstances and as clients under others, in a hierarchy of control and management functions, in addition to the primary mission of effecting communications. Certain components are relatively permanent in the network structure, yet others are intermittently part of the active network because they are mobile or remotely-operated. In addition, while many network components are "always on", others may be made dormant during periods of inactivity or maintenance. In view of the above, it is desirable that advanced high-bandwidth, high-performance, local bus adapters and controllers operate robustly and intelligently in most, if not all, environments, thereby forcing designers to make trade-offs between features and functionality, and available motherboard slots or board real estate.

The term "system manageability" represents technologies that enable remote system access and control in both OS-present and OS-absent environments. "OS-absent" is defined herein as a networked computer system being in a state including, without limitation, no active OS, inoperable OS, or low-power, system-sleep state. These technologies are primarily focused on minimizing on-site maintenance; maximizing system availability and performance to the local user; maximizing remote visibility of (and access to) local systems by network administrators; and minimizing the system power consumption required to keep this remote connection intact. Technologies that require the OS to be present do not allow an administrator to have remote visibility or access to systems that have serious hardware or software problems, which prevent the OS from loading or working correctly. In addition, such OS-present technologies do not allow for a system to be remotely managed while in a low-power mode.

Furthermore, computer processors typically communicate with cooperating components along one or more computer buses. Peripheral components, including audio, and print devices, portable storage media, and low bandwidth networking devices usually are coupled with the bus through a peripheral or expansion computer bus interface adapter. On the other hand, devices with high bandwidth needs, including video, memory, high-performance networking, and core storage media often are linked to the CPU via a high bandwidth local bus interface adapter. Components on expansion buses typically have operational speeds many orders of magnitude slower than that of the CPU; however, such components sporadically access CPU and system resources and, thus, critical design issues such as bus latency, setup & hold times, and clock-to-data time are of little import to interface adapters designed for those applications.

Although high-bandwidth, high-performance, local bus components and adapters tend to operate at clock speeds much higher than their expansion bus counterparts, they still lag current CPU speeds by about an order of magnitude. However, because local bus components tend to interact with the CPU to a significant degree, slow, inefficient, and poorly-designed local bus interface adapters can potentially waste substantial amounts of processor and system resources. Therefore, local bus interface adapters are usually faced with observing strict timing budgets when accessing and providing data to the local bus.

Many factors can lead an adapter to violate the timing budget imposed by a bus protocol. For example, delays introduced in the clock trees and in the data paths of bus adapters, or both, can effectively decouple the interface adapter from the bus, because the adapter response time fails to remain synchronized to the bus clock. The functional characteristics of VLSI devices employed in such high-bandwidth, high-performance computer bus interface adapters can be susceptible to design and process variations during manufacturing. Also, the response of such adapters can be compromised by variations in environmental conditions while operating.

There is a need, then, for a local bus interface adapter that mitigates critical path delays within a computer bus interface adapter, or device, to the extent that they do not violate the aforementioned timing budgets. It is desirable that such an adapter is robust to design and process variations during manufacturing, as well as to the environmental conditions, which may be encountered during operations. Because multiple local bus protocols exist in common computer environments, there also is a need for a robust, multiprotocol computer bus interface adapter that is observant of stringent bus protocol timing budgets. There also is a need for an advanced, high-performance, high-bandwidth local bus adapter/controller that integrates complex network communication, management, and support features and functions onto a single VLSI chip.

To reduce the total cost of ownership of computing systems such as personal computers, a number of technologies have been developed to provide more cost effective system maintenance and to maximize system "up-time". For example, some of these technologies give IT administrators more visibility and control over remote systems. Traditionally, these technologies require that the "managed" system is an operational state with the Operating System (e.g., Microsoft Windows.RTM.) of the computing system loaded. Examples of technologies that require the operating system ("OS") to be loaded are DMI and CIM.

In general, however, technologies that require the OS to be loaded do not allow an administrator to have remote visibility or access to systems that have serious hardware or software problems that prevent the OS from loading or working correctly. In addition, these technologies do not allow for a system to be remotely managed while in a low power mode. For these scenarios, there is a need for a standardized low-level technology that gives administrators remote access to and control over the managed system.

Several vendors have developed proprietary technologies in this area. Intel and IBM created Alert on LAN (AoL) technology. AoL provided remote notification of local system states and various hardware or software failures in an OS absent environment. In addition, Intel and others developed the Platform Event Trap ("PET") format, to describe how alerts were formatted over the network.

As the number of these technologies increased, computing system vendors were faced with the possibility of having to support several different alerting standards. As a result, the Distributed Management Task Force developed an open remote control and alerting standard: the Alert Standard Format ("ASF").

ASF is a specification that defines methods for alerting and remote system control. ASF is specifically targeted at OS-absent environments. As used herein, the term "OS-absent" refers to a computer system that is in a state including, without limitation, a no active OS state, an inoperable OS state, a low-power state, and/or a system-sleep state.

The remote control and alerting system defined by ASF includes a management system that communicates with one or more clients. Here, the term "client" refers to a managed computing system. Typically, the management system is located remotely from the computing systems and communicates with the clients via a network. An alert sending device ("ASD"), which is a component in each client, interfaces with other components in the computing system to respond to remote control requests from the management system. Such requests include, for example, power-up, power-down and maintenance requests. The ASD also interfaces with sensors in the client computing system. When a sensor detects an "alert event," the ASD in the client sends a corresponding alerting message to the management system. To this end, the ASF specification defines interfaces for sensors, alert sending devices (which may include, for example, network interface cards or Modems), remote management console software, and system firmware in order to allow system vendors (and system component vendors) to develop ASF compliant products.

In summary, the above technologies, collectively referred to as "system manageability" technologies, enable remote system access and control in both OS-present and OS-absent environments. These technologies are primarily focused on minimizing on-site maintenance; maximizing system availability and performance to the local user; maximizing remote visibility of (and access to) local systems by network administrators; and minimizing the system power consumption required to keep this remote connection intact.

While the technologies discussed above address some of the problems associated with "system manageability," they fall short of addressing many issued involved in providing a robust remote control and alerting system for computing systems. In particular, in networked computing systems, there is a need for a cost effect, yet highly high functional system for managing a computing system using standard protocols when the OS is not present.

SUMMARY OF THE INVENTION

An embodiment of the invention is a network controller. Included is a multiprotocol bus interface adapter coupled between a communication network and a computer bus. The adapter has a clock signal input, a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data, and a predictive time base generator coupled with the clock signal input and the data delay element. The time base generator has a predictive synchronizer having a synchronizing feedback loop therein, and a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay. The replica delay element causes the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay. An alert supervisory controller is coupled with the multiprotocol bus interface adapter, and is adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus.

An embodiment of the invention is in a network controller having a plurality of state machines receiving a plurality of inputs, effecting a plurality of predefined functions upon respective ones of the plurality of inputs, and producing a plurality of states thereby. An alert supervisory bus controller includes a processor operably coupled with the plurality of state machines and disposed to monitor the plurality of states and a rules-checker disposed to operate with the processor. The rules checker evaluates the plurality of states and identifies an alert supervisory state. The processor produces an predefined alert supervisory output responsive to the alert supervisory state.

An embodiment of the invention is also an alerting network controller which includes firmware coupled to an alert supervisory bus and bidirectionally translating data between an alert supervisory protocol and a network protocol. A network interface is coupled with the firmware and bidirectionally communicates the data between the firmware and a network implementing the network protocol.

The above needs can also be satisfied by providing an advanced, high-performance, high-bandwidth, highly-integrated controller that integrates complex network communication, management, and support features and functions onto a single VLSI chip. Embodiments of the invention can be realized as an Integrated Gigabit Ethernet PCI-X Controller. Embodiments of the invention may include a network controller coupled between a communication network and a computer bus which incorporates a multiprotocol bus interface adapter. The adapter has a clock signal input, a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data, and a predictive time base generator coupled with the clock signal input and the data delay element. The time base generator has a predictive synchronizer with a synchronizing feedback loop therein. It also has a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay, the replica delay element causing the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay and wherein the computer bus and the multiprotocol bus interface adapter are adapted to employ a PCI protocol, a PCI-X protocol, or both. An embodiment of the present invention may further include a management bus controller coupled with the multiprotocol bus interface adapter. The management bus controller is adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controlled is adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP). The invention also can include a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller (MAC) coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, or a combination thereof; and CPU, which may be used to transmit--in addition to other functions, and a CPU, which may be used to receive--in addition to other functions, coupled with the multiprotocol bus interface adapter and the management bus controller. The multiprotocol computer bus interface adapter, the management bus controller, or both can include at least one of a Gigabit Media Independent Interface (GMII) interface, an 10-Gigabit Media Independent Interface (XGMII), a 10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface (XAUI), a Serial Gigabit Media Independent Interface (SGMII), a Reduced Gigabit Media Independent Interface (RGMII), a Reduced Ten Bit Interface (RTBI), a Ten-Bit Interface (TBI), a Serial Gigabit Media Independent Interface (SMII), and a Media Independent Interface (MII). Also, the multiprotocol bus interface adapter is suited to interface one of an IEEE Std. 802.3-like protocol, a SONET/SDH-like protocol, a Fiber-Channel-like protocol, an SCSI-like protocol, and an InfiniBand-like protocol. Also, the predictive interface adapter may be a multiprotocol predictive interface adapter that can accommodate multiple computer bus protocols, including the PCI local bus protocol and the PCI-X local bus protocol, as well as similar bus protocols such as, for example, the CardBus protocol. Furthermore, local bus adapter/controller can be adapted to additionally accommodate at least one of the Alert Standard Format (ASF) specification protocol, the System Management Bus (SMBus) specification protocol, the Intelligent Platform Management Interface (IPMI) specification protocol, and the Simple Network Management Protocol (SNMP). In certain embodiments of the present invention, the network controller can be realized in a single-chip VLSI implementation, for example, an 0.18 micron CMOS VLSI implementation, which can be particularly advantageous for application of these embodiments to Gigabit Ethernet Network Interface cards and LAN-on-Motherboard (LOM) systems.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the present invention will be more fully understood when considered with respect to the following detailed description, appended claims and accompanying drawings, wherein:

FIG. 1 is a block schematic of an embodiment of a predictive time base generator according to the present invention, in the context of a predictive interface adapter for a computer bus;

FIG. 2 is a block schematic of an another embodiment of a predictive time base generator according to the present invention;

FIG. 3A is a block schematic of an embodiment of a PCI-X local bus predictive interface adapter employing a predictive time base generator, according to the present invention;

FIG. 3B is a block schematic of another embodiment of a PCI-X local bus predictive interface adapter employing a predictive time base generator, according to the present invention;

FIG. 4 is a simplified timing diagram illustrating timing characteristics of the predictive interface adapter in FIG. 3;

FIG. 5 is a block schematic of a embodiment of a multiprotocol PCI/PCI-X local bus predictive interface adapter employing a predictive time base generator, according to the present invention;

FIG. 6 is a simplified block schematic of a local area network controller, according to the present invention;

FIG. 7 is a simplified block schematic of an integrated, high-bandwidth local area network controller, according to the present invention;

FIG. 8 is a simplified block schematic of another embodiment of an integrated, high-bandwidth local area network controller, according to the present invention;

FIG. 9 is a simplified logic block schematic of an alerting network controller in the context of an alert management system;

FIG. 10 is a simplified block schematic of an alert management system having a multiprotocol controller according to the present invention; and

FIG. 11 is a simplified block schematic of an alert management system having an Integrated PCI-X controller according to the present invention.

DESCRIPTION OF THE EMBODIMENTS

The present invention implements an advanced, high-performance, high-bandwidth, highly-integrated controller, such as an Integrated Gigabit Ethernet PCI-X Controller, that integrates complex network communication, management, and support features and functions onto a single VLSI chip. Embodiments of the invention can be configured as a network controller, which is coupled between a communication network and a computer bus, and which incorporates a multiprotocol bus interface adapter and a alert supervisory bus controller.

To meet stringent timing requirements, whether in a computer bus interface adapter, or in another high-performance digital environment, the present invention provides a predictive time base generator that produces a predictive clock signal, typically advanced in time relative to an input clock signal, which can compensate for elements producing delays in a data path, a clock path, or both. It will be apparent to the skilled practitioner that the predictive time base generator of the present invention can be employed to compensate for critical path delays in applications other than computer bus interface adapters as well, and it is intended that the scope of the present invention include such applications. For example, within the domain of IEEE Std. 802.3-related network adapters, the predictive time base generator of the present invention can be employed advantageously in a myriad of interfaces including, without limitation, XGMII (10-Gigabit Media Independent Interface), XAUI (10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface), SGMII (Serial Gigabit Media Independent Interface), RGMII (Reduced Gigabit Media Independent Interface), RTBI (Reduced Ten Bit Interface), GMII (Gigabit Media Independent Interface), as well as in TBI, SMII, and MII interfaces. IEEE Std. 802.3, 2000 Edition, CSMA/CD Access Method and Physical Layer Specifications, relevant to such implementations, is hereby incorporated herein in its entirety.

FIG. 1 illustrates one embodiment of the invention herein, in which predictive interface adapter (PIA) 100 is interposed in data path 120, 125 between data source 105, and data sink 110, of communication system 101. PIA 100 can include a data delay element, here buffer 115, and predictive time base generator (PTBG) 130. For purposes of illustration, the relevant preselected edge of clock signal 145 will be defined as the arriving rising edge. Assuming valid data is available on data output path 120, prior to the arriving edge of clock signal 145, direct clocking of buffer 115 by input clock signal 145 would impose a delay upon data propagating through buffer 115 from data path 120 to data path 125. In this case, the period between the arriving rising edge of clock signal 145 to valid data out on path 125 would be extended by the predetermined data delay through delay element 115. On the other hand, by providing an early clock signal, relative to the rising edge of clock signal 145, buffer 115 can be clocked after data is valid on data path 120 but before the actual arrival of the rising edge of clock signal 145, substantially nullifying the predetermined data delay, and minimizing the period between the rising edge of clock signal 145 to valid data out on data path 125.

In order to provide such an early clock signal, PTBG 130 provides a predictive clock signal 155 to buffer 115. PTBG 130, according to the present invention, can include a predictive synchronizer 135, which receives input clock signal 145 and, through, delay feedback 150, produces signal 155 substantially locked with, but advanced relative to, clock input signal 145. In general, it is preferred that synchronizer 135 be a phase lock loop (PLL), although a delay lock loop (DLL) also may be used. By inserting replica delay element 140 between synchronizer output 155 and delay feedback 150, synchronizer 135 can lock with input clock signal 145 such that predictive signal 155 is advanced, relative to signal 145, by an amount of time substantially replicating the predetermined data delay imposed by delay element 115. Thus, valid data can be made available on path 125 essentially simultaneously with the arriving rising edge of clock signal 145, and PTBG 130 assists with data synchronization as well as providing a predictive timing signal. It is generally preferred to replicate the structure(s) inducing the critical data path delay within replica delay element 140, in order to obtain an accurate and robust approximation of the predetermined data delay. Advantageously, the approximation of the predetermined data delay thus obtained is largely unaffected by variations in design and fabrication processes, operating environment, and the like.

In many applications, a data path delay can be accompanied by a clock-related delay, for example, a clock tree delay. Thus, PIA 200 in FIG. 2 is adapted to additionally compensate for clock-related delays in internal clock path producing delayed clock signal 265. Similar to the structure and function described with regard to FIG. 1, PIA 200 is interposed between data source 205 and data sink 210, in communication system 201. PIA 200 includes PTBG 230, which provides predictive clock signal 255 to data delay element 215. As before, a predetermined data delay exists within PIA 200, as indicated by data delay element 215.

However, in PIA 200, an additional source of delay is encountered, namely, a predetermined clock delay in the propagation of input clock signal 245, which clock delay is modeled by clock delay element 260. In order to compensate for both types of delays, it is desirable to adapt replica delay element 230, which is coupled with delay feedback 250, to replicate therein both data delay element 215 and clock delay element 260. In this manner, predictive synchronizer 235 produces predictive clock signal 255 advanced in time, relative to input clock signal 245, to substantially nullify both the predetermined data delay and the predetermined clock delay.

In operation, interface block 270 receives data on data path 220 from data source 205. This data is made available on data path 275 to data delay element 215 before the arrival of the preselected (e.g., rising) edge of input clock signal 245. Were data delay element 215 to be clocked by delayed clock signal 265, the resultant delay from clock 245 to valid data out on data path 225 would be approximately the sum of the predetermined data delay and the predetermined clock delay. Because the clock-to-valid-output-data delay is typically one of the most difficult timing constraints to meet in such a device, direct clocking by delayed clock signal 265 may cause a standard interface adapter to violate, or undesirably approach, the relevant timing restriction. Thus, it is preferred that predictive clock signal 255 clocks data delay element 215 in advance of the arrival of input clock signal 245 such that valid data is available on data path 225 at, or desirably near, the arrival of the rising edge of input clock signal 245 to PIA 200.

In the event that wire delays represent significant components in the data delay, the clock delay, or both, a compensatory replica wire delay element 280, corresponding to the undesirable wire delays, can be incorporated with delay element 230 in the path of feedback delay 250. Moreover, interface block 270 can be a component that selectively transfers data in a manner suitable to one or more computer bus protocols, and thus PIA 200 can be a multiprotocol predictive interface adapter.

The embodiments of the present invention illustrated in FIG. 1 and FIG. 2 can be used in a variety of devices in which it is desired to reduce the effects of signal propagation delay, for example, in a computer network or in a computer system. Such computer network components, for example, network time synchronizers and Serializer-Deserializers (SERDES), can be adapted for applications related to exemplary networking protocols including, without limitation, Ethernet, SONET/SDH, Fibre Channel, Ultra3 SCSI, InfiniBand, and the like.

Certain preferred embodiments of the invention herein can be especially advantageous when used in conjunction with particular computer bus interface adapters, particularly where multiple bus protocols are employed. Such an application can based, for example, on the Peripheral Component Interconnect (PCI) Local Bus specification and its subsequent enhancements. A skilled artisan would realize, however, that the present invention also can readily be adapted for bus implementations similar to the PCI Local Bus, including, without limitation, CardBus implementations. CardBus is a 32-bit bus mastering interface defined by the PC Card Standard, Release 8, March 1997, and by the PCI to PCMCIA CardBus Bridge Register Description (Yenta specification--Intel Corporation) which standards are incorporated herein in their entirety.

It will be useful to briefly describe the PCI bus family of protocols in order to inform the subsequent descriptions of additional embodiments of the invention, as realized in the context of the PCI/PCI-X bus protocols. The PCI specification was introduced to define a low-latency path between the microprocessor local bus and faster peripherals, such as high-resolution video boards, disk controllers, and LAN devices. The original PCI bus specification (PCI33) defines a 33 MHz, 32-bit or 64-bit data path to achieve a bandwidth of about 133 Mbps. Later, the 66 MHz PCI (PCI66) bus was introduced as a compatible superset of PCI33. A PCI66 bus operates up to a maximum clock speed of 66 MHz, also using a 32-bit or 64-bit data path, providing a peak bandwidth of about 533 megabytes per second (MB/s). Differences between the PCI33 bus and the PCI66 bus are minimal: PCI66 utilizes the PCI33 bus protocol, signal definitions, and connector layout, and simply operates at a higher maximum bus clock frequency. The PCI66 bus is specified to be interoperable with the PCI33 bus; a PCI66 device operates as a PCI33 device when it is connected to a 33 MHz PCI bus. Similarly, if any PCI33 devices are connected to a PCI66 bus, the PCI66 bus operates as if it were a PCI33 bus. PCI33 devices are specified to operate between 0 33 MHz and PCI66 devices between 33 66 MHz.

However, despite the advantages of the PCI66 protocol, business-critical applications continue to demand greater bandwidth, and shorter response times, from the input/output (I/O) subsystems of enterprise computers. Faster and more complex I/O devices such as Gigabit Ethernet, Fibre Channel, Ultra3 SCSI, and multi-port network interface controllers (NICs) can demand far greater bandwidth than PCI33, or PCI66, can provide. For example, a four-port Gigabit Ethernet NIC, with each port capable of 1 gigabit-per-second, or 125 MB/s, of sustained throughput would overwhelm the 64-bit, 66-MHz PCI bus bandwidth by consuming essentially all available bandwidth. Thus, the conventional PCI bus technology can become a performance bottleneck. To break this I/O bottleneck, the PCI-X bus was developed as an enhancement of t