A nonvolatile memory device features a hybrid switch cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a hybrid switch. The hybrid switch cell comprises a ferroelectric capacitor and a hybrid switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The hybrid switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a hybrid switch cell comprises a plurality of hybrid switch cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of hybrid switch cell arrays each includes a single hybrid switch cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.
A nonvolatile memory device using a hybrid switch cell comprises a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a main bit line and a sub bit line. In the nonvolatile memory device, each sub cell array having the hierarchical bit line structure including a main bit line and a sub bit line is provided as a cross point cell array that comprises a nonvolatile ferroelectric capacitor and a hybrid switch which does not require an additional gate control signal, thereby reducing the whole memory size.
One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor includes a first semiconductor fin having a first conductivity type and overlying a semiconductor body, a dielectric overlying at least part of the semiconductor fin, and a gate electrode overlying the dielectric. The memory cell also includes a diode. The diode includes an end portion of the first semiconductor fin and a second semiconductor fin that forms a junction with the end portion of the first semiconductor fin. The second semiconductor fin has a second conductivity type and includes first and second legs in different directions from the junction. Other devices and methods are also disclosed.
