A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks.
A defect address storing circuit for a semiconductor memory device comprises a plurality of fuse pairs formed in a fuse region and a plurality of transistors formed in a transistor region outside the fuse region. The plurality of fuse pairs and the plurality of transistor pairs are arranged to form a continuous current path through at least one fuse in each of the plurality of fuse pairs, and through at least one transistor in each of the plurality of transistor pairs.
A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, the first node is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.
A repair I/O fuse circuit of a semiconductor memory device includes a reduced by as much as half layout area of fuses by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse. The repair I/O fuse circuit includes a plurality of I/O fuse circuits, each having one fuse. A repair signal indicates that there is an address to be replaced. If a chip enable signal is activated, each of the plurality of I/O fuse circuits outputs a repair I/O information signal depending on whether a fuse has been cut.
