A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.
CROSS REFERENCE TO RELATED DOCUMENTS
This application is related to U.S. patent application Ser. No. 09/975,115, to Warren Snyder, et al., entitled "IN-SYSTEM CHIP EMULATOR ARCHITECTURE"; and to U.S. patent application Ser. No. 09/975,104, to Warren Snyder, entitled "CAPTURING TEST/EMULATION AND ENABLING REAL-TIME DEBUGGING USING AN FPGA FOR IN-CIRCUIT EMULATION"; and to U.S. patent application Ser. No. 09/975,338, to Warren Snyder, et al., entitled "METHOD FOR BREAKING EXECUTION OF (TEST) CODE IN A DUT AND EMULATOR CHIP ESSENTIALLY SIMULTANEOUSLY AND HANDLING COMPLEX BREAKPOINT EVENTS"; and to U.S. patent application Ser. No. 09/975,105, to Craig Nemecek entitled "HOST TO FPGA INTERFACE IN AN IN-CIRCUIT EMULATION SYSTEM". Each of these applications is filed on the same date as the present application and is hereby incorporated by reference as though disclosed fully herein. This application is also related to and claims priority benefit under 35 U.S.C. .sctn. 119(e) of provisional patent application Ser. No. 60/243,708 filed Oct. 26, 2000 to Snyder, et al. entitled "Advanced Programmable Microcontroller Device" which is hereby incorporated herein by reference.
Device emulation implemented in programmable circuits. In one aspect, an interface for providing control of a hardware device includes functional code embedded in circuitry of the interface. Emulator code is embedded in programmable circuitry of the interface to emulate the hardware device during testing of the functional code and the interface. Another aspect diagnoses errors in a system having an interface and a connected hardware device, using emulator code embedded in a programmable circuit of the interface.
A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE (in-circuit emulation) to form a virtual microcontroller. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code for debugging purposes. The microcontroller residing on a test circuit includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. Software in the host device compares the content of the first memory and the content of the second memory for consistency. In case of a disparity between the content of the first memory and the content of the second memory, a user traces the execution of the code in a trace buffer residing in the ICE and debugs the faulty code accordingly.
