An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of U.S. application Ser. No. 10/307,638, filed Dec. 2, 2002, now U.S. Pat. No. 6,754,777, which is a divisional of U.S. application Ser. No. 09/721,478, filed Nov. 22, 2000, now U.S. Pat. No. 6,546,461, the disclosures of which are hereby incorporated herein by reference.
