An electronic circuit, having a test mode in application of the "internal scan path" technique, includes a plurality of configurable cells and a control circuit. The electronic circuit is adapted to working in a standard mode of operation or in a test mode during which the control circuit is active and configures the configurable cells either in a functional state or in a chained state. The electronic circuit furthermore includes a validation circuit that performs the following operations successively when it receives an instruction for changing the mode of operation (TEST, FIN) of the electronic circuit: produce initialization signals (INIT1, INIT2, . . . , INITN) to command the initialization of all the configurable cells, and then produce a mode-changing signal (VAL).

An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

An electronic circuit includes a plurality of configurable cells configured by a control circuit such as a test access controller when it receives a mode command signal: either in a functional state in which the configurable cells are functionally linked to logic cells with which they co-operate to form at least one logic circuit if the mode command signal is in a first state or in a chained state in which the configurable cells are functionally connected in a chain to form a shift register, if the mode command signal is in a second state. The electronic circuit also includes a detection circuit laid out to produce an active state signal if it detects a chained state of the configurable cells while the controller receives the mode command signal in the first state.

A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control circuit that controls the non-volatile memory core and the test data input buffer. The control circuit is configured to load test data from the test data buffer to the page buffer, to program the loaded test data in the page buffer in the memory cell array, and to retain the test data in the page buffer for subsequent programming of the memory cell array. The device may further include a test data output buffer configured to receive data read from the memory cell array, and the control circuit may be operative to convey the read data from the test data output buffer to an external recipient.

An electronic circuit comprises a plurality of configurable cells configured according to a chaining command signal. These configurable cells are configured either in a chained state in which the configurable cells are functionally connected in a chain to form a shift register, if the chaining command signal is in a first state, or in a functional state in which the configurable cells are functionally linked to logic cells with which they co-operate to form at least one logic circuit, if the mode command signal is in a second state. It is provided that a test data word will be preceded by a signature. The set formed by the digital signature and the data word forms a test sequence. The signature is verified before the introduction of the test data word by an appropriate detection circuit.