A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
PRIORITY CLAIM
This application claims the benefit of U.S. Provisional Appl. Nos. 60/358,133 and 60/358,290, both filed on Feb. 19, 2002, the disclosures of which are hereby incorporated by reference.
Methods of operating an integrated circuit memory device include providing a first address and a first command to the memory device and executing the first command within the memory device. This step of executing the first command is performed concurrently with providing at least one of a second address and a second command to the memory device prior to terminating execution of the first command. This providing of at least one of the second address and the second command prior to termination execution of the first command improves timing efficiency by reducing delay associated with execution of each new command.
An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.
In a method of accessing a single port memory, a plurality of read commands are received from a plurality of requestors for memory read access. A respective plurality of parameters corresponding to each of the plurality of read commands is stored in a memory read command queue. The parameters corresponding to one of the read commands are retrieved from the memory read command queue when the single port memory provides the data corresponding to that read command. One or more of the parameters from the memory read command queue are provided while providing the data from the memory.
