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Method for forming flowable dielectric layer in semiconductor device
   
Document Number
US Patent 7087515
Issued Date
August 8, 2006
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Abstract
A method for forming a flowable dielectric layer using a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs. The method includes steps of: forming patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out an annealing process for densifying the flowable dielectric layer and removing moisture therein; forming contact holes by selectively etching the flowable dielectric layer so as to expose predetermined portions of the semiconductor substrate; forming a barrier layer on sidewalls of the contact holes for preventing micro-pores in the flowable dielectric layer; carrying out a cleaning process in order to remove native oxides and defects on the semiconductor substrate; and forming contact plugs by filling a conductive material into the contact plugs.
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Number of Claims:
8
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Published
August 8, 2006
Application Number
10/741,791
Filed
December 19, 2003
US Classification
438/618   438/778
Int'l Classification
H01L   21/02   (20060101)   H01L   21/283   (20060101)  
Examiner
Priority Data
Jul 24, 2003 [KR] 10-2003-0051127
USPTO Field of Search
438/618   438/778  
Related Patents
7220668 - Method of patterning a porous dielectric material - Owned by Intel Corporation (Santa Clara, CA)

A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.

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