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Document Number
US Patent 7092042
Issued Date
August 15, 2006
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Abstract
A PLL circuit compares a PCR with the output frequency of a voltage controlled oscillator (VCO), and returns a voltage value which is the result of the comparison to the VCO, so that a reference clock corresponding to the PCR is outputted from the VCO. A switch supplies a control voltage from the PLL circuit to the VCO when digital broadcasting is viewed, while feeding a fixed voltage from a fixed voltage power supply to the VCO when analog broadcasting is viewed, to stably output a clock having a frequency of 27 MHz irrespective of the change in the PCR.
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Number of Claims:
4
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Published
August 15, 2006
Application Number
10/443,062
Filed
May 22, 2003
US Classification
348/725   348/505 348/509 348/706 348/730
Int'l Classification
H04N   3/27   (20060101)  
Examiner
Priority Data
May 24, 2002 [JP] 2002/150440
USPTO Field of Search
348/725   348/726   348/727   348/728   348/725   348/726   348/727   348/728   348/725   348/726   348/727   348/728   348/505   348/549  
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7443451 - Display device for simultaneously receiving digital signal and analog display signal - Owned by Tatung Co., Ltd. (Taipei,TW)

A display device can simultaneously receive digital display signal and analog display signal and display a television program corresponding to one of the signals on a display panel. The display device includes the following components: a digital tuner, an analog/digital converter, a video decoder, an audio decoder, a de-interlacer, a scaler, a display driver, a display panel, an audio amplifier, and a speaker. The display device allows the user to watch a television program corresponding to the digital display signal or the analog display signal on the display panel and listen to amplified television audio signal from the speaker.

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Description
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