A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.
This application claims the benefit of U.S. Provisional Application Ser. No. 60/432,168 filed on Dec. 10, 2002, U.S. Provisional Application Ser. No. 60/436,960 filed on Dec. 30, 2002, and U.S. application Ser. No. 10/654,501 entitled "Methods and Apparatus for Modular Reduction Circuits" filed concurrently, all both of which are incorporated by reference herein in their entirety.
A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.
Systems and methods are described for high-speed memory assignment schemes for routing packets in a sharable parallel memory module based switch system. A method includes receiving a parameter, determining availability of memory location, determining if an available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available. Systems of the present invention provides hardware and/or software based components for implementing the steps of receiving a parameter, determining available memory location, determining if available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available.
Methods and apparatus are disclosed for defining flow types and instances thereof such as for identifying packets corresponding to instances of the flow types. A flow type is defined and includes a set of properties including at least one of the possible properties selectable when defining a flow type. An instance of the flow type is defined and a set of corresponding associative memory entries is generated. A lookup word generator of a packet processing engine is typically notified of the use of the flow type, and one or more lookup words are generated typically by extracting fields from a received packet and/or from other sources. Based on a result of lookup operations on the set of associative memories entries using the generated one or more lookup words, the received packet can be identified as whether it matches or does not match the instance of the flow type.
