An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/843,119, filed Apr. 26, 2001, now U.S. Pat. No. 6,634,100, issued Oct. 21, 2003, which is a divisional of application Ser. No. 09/533,407, filed Mar. 23, 2000, now U.S. Pat. No. 6,529,027, issued Mar. 4, 2003.
The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side walls formed around the base. In the step-to-step carriage in the post-production process of the manufacture of wafer level CSPs and on like occasions, the base supports not the organic film but the plurality of solder bumps. For this reason, it is made possible to prevent the organic film from being flawed or coming off and adhering to the product as foreign matter, and as a result the quality and yield of the wafer level CSPs (semiconductor devices) can be improved.
An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
A surface mount connector and assembly including the surface mount connector is shown and described. The assembly comprises a substrate and a connector including a carrier, and at least one electrical connecting element having first and second ends, wherein at least a portion of the first end extends through the carrier to electrically adjoin and physically secure the connector to the substrate. A reinforcement medium is disposed about at least a portion of surface mount connector and said substrate.
