Simplifying the design of buffer amplifier circuits to provide reference voltages of desired characteristics on a path. Two separate circuits may be used to provide the necessary charging (of a load connected to the path) in non-overlapping time durations. In an embodiment in which the load comprises sampling capacitors of a stage of an analog to digital converter (ADC), each of the two circuits contains a corresponding charging capacitor, with the charging capacitors charging the load in non-overlapping time durations of a hold phase. The first charging capacitor may be charged using a coarse buffer with a high drive strength and the second charging capacitor may be charged using a fine buffer with high accuracy.
According to an aspect of the present invention, samples of an input signal are provided with reduced distortion, when the input signal is received from a lead terminal offering lead inductance on an input path. Such a feature is achieved by charging a energy storage element to a value proportional to the input signal using a portion of charging energy received through a path having less lead inductance compared to the path connecting the input signal to the energy storage element. Thus, the energy drawn through the lead impedance is reduced, thereby reducing the magnitude of the distortion caused.
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.
A digital-to-analog data converter for converting a digital input signal to an analog output signal is provided. The digital-to-analog data converter includes a register, a decoder, a converting unit and an output unit. During a first period, the decoder decodes least significant bits, and takes the decoded least significant bits as a first control signal for controlling the converting unit to output a first converting current according to the first control signal. During a second period, the decoder decodes most significant bits, and takes the decoded most significant bits as a second control signal for controlling the converting unit to output a second converting current according to the second control signal. The output unit registers the first converting current during the first period, amplifying the second converting current, and combining the amplified second converting current with the registered first converting current as the analog output signal during the second period.
