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Testing of integrated circuit devices    

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United States Patent7103815   
Link to this pagehttp://www.wikipatents.com/7103815.html
Inventor(s)Ong; Adrian E. (Pleasanton, CA), Ho; Fan (San Ramon, CA)
AbstractAn integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
   














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Patent Text Patent PDF Print Page Summary File History
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Inventor     Ong; Adrian E. (Pleasanton, CA) , Ho; Fan (San Ramon, CA)
Owner/Assignee     Inapac Technology, Inc. (San Jose, CA)
Patent assignment
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Company News
Publication Date     September 5, 2006
Application Number     10/870,365
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     June 17, 2004
US Classification     714/736 713/401 714/819
Int'l Classification    
Examiner     Tu; Christine T.
Assistant Examiner    
Attorney/Law Firm     Sidley Austin LLP
Address
Parent Case     RELATED APPLICATION The present application is a continuation of U.S. patent application Ser. No. 09/967,389, filed Sep. 28, 2001, now U.S. Pat. No. 6,754,866, which is related to U.S. Pat. No. 6,732,304, filed Sep. 21, 2000, both of which are assigned to the present assignee and hereby incorporated by reference in their entireties.
Priority Data    
USPTO Field of Search     714/736 714/814 714/819 714/738 714/798 714/799 714/724 714/824 714/718 714/719 713/400 713/401 713/500 713/600 324/210 324/211 324/212
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 U.S. References
 
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