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Rail-to-rail delay line for time analog-to-digital converters
   
Document Number
US Patent 7106239
Issued Date
September 12, 2006
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Abstract
A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.
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Rail-to-rail delay line for time analog-to-digital converters - US Patent 7106239 Drawing
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Number of Claims:
8
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Owner
Qualcomm Incorporated (San Diego, CA)
Published
September 12, 2006
Application Number
11/197,172
Filed
August 3, 2005
US Classification
341/157   341/155
Int'l Classification
H03M   1/60   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
341/157  
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