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Method of manufacturing a semiconductor integrated circuit device
   
Document Number
US Patent 7109126
Issued Date
September 19, 2006
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Abstract
In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than the resolution limit for the exposure light.
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Number of Claims:
21
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Owner
Published
September 19, 2006
Application Number
10/855,598
Filed
May 28, 2004
US Classification
438/737   438/672
Int'l Classification
H01L   21/302   (20060101)   H01L   21/461   (20060101)  
Examiner
Priority Data
May 30, 2003 [JP] 2003-153882
USPTO Field of Search
438/241   438/253   438/396   438/656   438/672   438/697   438/737  
Related Patents
7285467 - Methods of fabricating static random access memories (SRAMS) having vertical transistors - Owned by Samsung Electronics Co., Ltd. (KR)

Unit cells of a static random access memory (SRAM) are provided including an integrated circuit substrate and first and second active regions. The first active region is provided on the integrated circuit substrate and has a first portion and a second portion. The second portion is shorter than the first portion. The first portion has a first end and a second end and the second portion extends out from the first end of the first portion. The second active region is provided on the integrated circuit substrate. The second active region has a third portion and a fourth portion. The fourth portion is shorter than the third portion. The third portion is remote from the first portion of the first active region and has a first end and a second end. The fourth portion extends out from the second end of the third portion towards the first portion of the first active region and is remote from the second portion of the first active region. Methods of forming SRAM cells are also described.

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