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Document Number
US Patent 7110279
Issued Date
September 19, 2006
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Abstract
A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.
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Number of Claims:
25
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Owner
Published
September 19, 2006
Application Number
10/935,554
Filed
September 8, 2004
US Classification
365/145   365/149
Int'l Classification
G11C   11/22   (20060101)   G11C   11/24   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Sep 11, 2003 [JP] 2003-319483 Apr 22, 2004 [JP] 2004-126244
USPTO Field of Search
365/145   365/149   365/185.02   365/194   365/233   365/233.5  
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7558098 - Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials

A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.

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Description
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