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Reducing the effect of noise present along with an input signal when sampling the input signal
   
Document Number
US Patent 7113117
Issued Date
September 26, 2006
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Abstract
An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several parallel connected capacitors for different time durations with at least some non-overlap. In an embodiment, such an approach is used in a switched capacitor amplifier circuit of an ADC. The capacitors in that embodiment start charging at the same time instance, but stop charging at different time instances due to the design of associated switches and control signals.
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Reducing the effect of noise present along with an input signal when sampling the input signal - US Patent 7113117 Drawing
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Number of Claims:
20
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Owner
Published
September 26, 2006
Application Number
11/163,101
Filed
October 5, 2005
US Classification
341/123   341/122
Int'l Classification
H03M   1/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
341/123   341/118   341/122  
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7339512 - Analog-to-digital converter without track-and-hold - Owned by Edgewater Computer Systems, Inc. (Kanata, Ontario,CA)

A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.

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