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Method and apparatus for optimizing timing for a multi-drop bus
   
Document Number
US Patent 7117401
Issued Date
October 3, 2006
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Abstract
A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.
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Number of Claims:
20
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Owner
Intel Corporation (Santa Clara, CA)
Published
October 3, 2006
Application Number
11/121,789
Filed
May 4, 2005
US Classification
714/715   714/709 714/738
Int'l Classification
H04L   1/24   (20060101)  
Parent Case
The present application is a Continuation of application Ser. No. 10/187,349, filed Jun. 28, 2002, now U.S. Pat. No. 6,973,603 entitled "Method and Apparatus for Optimizing Timing for a Multi-Drop Bus", and claims priority thereof.
USPTO Field of Search
714/738  
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