A semiconductor memory device is provided which includes: a plurality of memory cells each formed by latch means; gated clock circuits for writing identical data to all of the memory cells in response to a simultaneous writing signal supplied thereto; inverters for inverting data outputted from the memory cells; and selectors for selectively writing the inverted data to the memory cells.
A memory device includes a memory cell array to store data, a register to store test data, and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to the data, the test data, and the inverted test data.
