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Method for fabricating semiconductor device
   
Document Number
US Patent 7122467
Issued Date
October 17, 2006
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Abstract
Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.
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Number of Claims:
13
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Owner
Published
October 17, 2006
Application Number
10/879,733
Filed
June 30, 2004
US Classification
438/637   438/672 438/970
Int'l Classification
H01L   21/4763   (20060101)  
Priority Data
Dec 22, 2003 [KR] 10-2003-0094700
USPTO Field of Search
438/637   438/672   438/970  
Related Patents
7410866 - Method for forming storage node of capacitor in semiconductor device - Owned by Hynix Semiconductor Inc. (Icheon-si,KR)

A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.

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