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Document Number
US Patent 7122875
Issued Date
October 17, 2006
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Abstract
A p well serving as a channel region of a MOSFET is formed on one side of an n.sup.- layer and an n.sup.+ drain region is formed on the other side. Above the n.sup.- layer, a plurality of first floating field plates are formed with a first insulating film interposed therebetween. A plurality of second floating field plates are formed thereon with a second insulating film interposed therebetween. Assuming that the thickness of the first insulating film is "a" and the distance between the first floating field plates and the second floating field plates in a direction of thickness of the second insulating film is "b", a relation a>b is held.
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Number of Claims:
20
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Published
October 17, 2006
Application Number
10/998,983
Filed
November 30, 2004
US Classification
257/488   257/49 257/E29.009
Int'l Classification
H01L   23/58   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Jan 26, 2004 [JP] 2004-016663
USPTO Field of Search
257/487   257/488   257/490   257/491   257/492   257/493   257/494   257/495   257/496   257/327   257/341   257/342   257/367   257/347   257/77   257/129  
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