A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of Ser. No. 09/420,086 filed Oct. 18, 1999, U.S. Pat. No. 6,979,898, which is a division of Ser. No. 09/110,232, filed Jul. 06, 1998, U.S. Pat. No. 6,107,119.
