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Memory protection system and method for computer architecture for broadband networks
   
Document Number
US Patent 7139882
Issued Date
November 21, 2006
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Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
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Number of Claims:
11
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Published
November 21, 2006
Application Number
10/371,322
Filed
February 21, 2003
US Classification
711/153   711/148 711/173
Int'l Classification
G06F   12/00   (20060101)  
Examiner
Parent Case
CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of commonly assigned, U.S. patent application entitled "Memory Protection System and Method for Computer Architecture for Broadband Networks," application Ser. No. 09/816020, filed Mar. 22, 2001 now U.S. Pat. No. 6,526,491; the disclosure of which is incorporated by reference herein.
USPTO Field of Search
711/147   711/153   711/148   711/173  
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