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Semiconductor device, method of manufacturing three-dimensional stacking type semiconductor device, circuit board, and electronic instrument
   
Document Number
US Patent 7141493
Issued Date
November 28, 2006
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Abstract
A semiconductor device has a substrate and an electrode layer formed on the substrate, and the electrode layer includes a plurality of conductive layers and an insulating layer which are stacked, the insulating layer being interposed between two of the conductive layers adjacent each other, a through-hole being formed in each of the conductive layers lower than an uppermost conductive layer among the conductive layers, and the through-hole being filled with an insulating material.
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Number of Claims:
1
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Published
November 28, 2006
Application Number
10/799,621
Filed
March 15, 2004
US Classification
438/618  
Int'l Classification
H01L   21/4763   (20060101)  
Assistant Examiner
Attorney/Law Firm
Priority Data
Mar 27, 2003 [JP] 2003-088825 Dec 22, 2003 [JP] 2003-424713
USPTO Field of Search
438/15   438/104   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/135   438/142   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/151   438/157   438/176   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/637   438/667   438/406   438/455   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/107   438/108   438/109   438/110   438/111   438/112   438/113   438/114   438/620  
Related Patents
7436069 - Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode - Owned by NEC Electronics Corporation (Kanagawa,JP)

The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.

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Description
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