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Current mirror with low headroom requirement
   
Document Number
US Patent 7161432
Issued Date
January 9, 2007
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Abstract
A current mirror circuit includes a current input node for receiving an input current, an upper, cascoded current mirror, a lower current mirror, and a biasing means. In a FET implementation, the upper mirror includes first and second cascoded FETs which are connected together at the current input node, and third and fourth cascoded FETs connected to mirror the current conducted by the first and second FETs. The lower current mirror receives the mirrored current and mirrors it back to the upper mirror, thereby providing positive feedback. The net loop gain is between zero and one. When so arranged, the third and fourth FETs conduct a current which is proportional to an applied input current. The upper mirror transistors are biased such that the voltage at the current input node is substantially closer to the supply voltage than the voltages at the gates of the first and third FETs.
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Number of Claims:
18
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Owner
Analog Devices, Inc. (Norwood, MA)
Published
January 9, 2007
Application Number
11/108,990
Filed
April 18, 2005
US Classification
330/288  
Int'l Classification
H03F   3/04   (20060101)  
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Assistant Examiner
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