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SOI single crystalline chip structure with multi-thickness silicon layer
   
Document Number
US Patent 7173309
Issued Date
February 6, 2007
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Inventors
Chien; Ray (Hsin Tien,TW)
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Abstract
A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a second silicon layer is located below the first silicon layer and the buried oxide area.
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Number of Claims:
20
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Owner
Via Technologies Inc. (Taipei Hsien,TW)
Published
February 6, 2007
Application Number
10/834,263
Filed
April 29, 2004
US Classification
257/347   257/499 257/E21.563 257/E21.703 257/E27.112
Int'l Classification
H01L   27/01   (20060101)  
Examiner
Assistant Examiner
Priority Data
Apr 29, 2003 [CN] 03246541 Apr 29, 2003 [CN] 03246542
USPTO Field of Search
257/499   257/347   257/301   257/302   257/329   257/330   257/350   257/349   257/352   257/353   257/354   257/E27.112   257/E21.563   438/405   438/407  
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