Tiered built-in self-test (BIST) architecture for testing distributed memory modules

The invention claimed is:

1. A system comprising: a plurality of memory modules, at least one memory module having a clock domain different that other of said plurality of memory modules; a single built-in self-test (BIST) controller that stores an algorithm for testing the memory modules; and a plurality of sequencers, each sequencer coupled to a different subset of the memory modules, wherein each subset of the memory modules is selected to include the memory modules having common clock domains, and each sequencer controls the application of the test algorithm to the respective subset of memory modules in accordance with the common clock domain of that subset of memory modules.

2. The system of claim 1, wherein the sequencer controls an application speed of the memory operations to the memory interface in accordance with timing requirements of the memory module.

3. The system of claim 1, wherein the sequencer comprises: a plurality of command controllers that implement the commands in accordance with a command protocol; and a command parser to parse each command to identify an operational code and a set of parameters based on the command protocol, wherein the command parser selectively invokes the command controllers based on the operational codes of the commands received from the BIST controller.

4. The system of claim 3, wherein when invoked the command controllers issue the memory operations to the memory interface by sequencing through address ranges defined by the respective commands.

5. The system of claim 3, wherein the command controllers issue the memory operations by asserting signals to apply addresses and data to the memory interface based on the commands received from the BIST controller.

6. The system of claim 5, wherein the command controllers issue the memory operations by further asserting control signals to direct the memory interface to automatically store inverted data between at least one of neighboring rows, neighboring columns, and neighboring row-column matrices based on the physical characteristics of the memory module.

7. The system of claim 5, wherein based on the physical characteristics of the memory module the memory interface translates the addresses specified by the sequencer for the memory operations.

8. The system of claim 7, wherein the memory module includes memory cells arranged in rows and columns, and the memory interface translates the addresses to fill the memory module in a row-wise or column-wise fashion as specified by the commands from the BIST controller.

9. The system of claim 5, wherein the commands specify a bit pattern to be written to the memory module, and the memory interface translates the data specified by the sequencer based on the specified bit pattern and the physical characteristics of the memory module.

10. The system of claim 1, wherein the memory interface comprises a data generation unit that receives data signals from the sequencer and generates transformed data signals based on the data signals and the physical characteristics of the memory module.

11. The system of claim 10, wherein, in response to a control signal received from the sequencer, the data generation unit automatically transforms the data to store inverted data within at least one of neighboring rows, neighboring columns, and neighboring row-column matrices of the memory module.

12. The system of claim 1, wherein the memory interface comprises an address generation unit that receives address signals from the sequencer and generates transformed address signals applied based on an arrangement of rows and columns of the memory module.

13. The system of claim 1, wherein the memory interface comprises a comparator to compare data read from the memory module to data previously written to the memory module and set a state of a failure signal based on the comparison.

14. The system of claim 1, wherein the physical characteristics include at least one of a number of rows, a number of columns, and a number of row-column matrices of the memory module.

15. The system of claim 1, wherein the commands conform to a generalized command protocol that substantially defines the test algorithm without regard to physical characteristics and timing requirements of the memory module.

16. The system of claim 15, wherein the command protocol defines a command syntax having a set of supported commands, and each command includes an operand and a set of parameters.

17. The system of claim 16, wherein at least one of the commands includes fields to specify an address range, one or more memory operations to apply over the address range, and a bit pattern for application to the memory module of the address range.

18. The system of claim 1, wherein the BIST controller, memory interface and sequencer are integrated within an electronic device.

19. The system of claim 1, further comprising a plurality of memory interfaces that are respectively coupled to the memory modules, wherein each of the memory interfaces receive address and data signals generated by the sequencer based on the algorithm and translates the address and data signals in accordance with an arrangement of rows and columns of the respective memory module.

20. A system comprising: a plurality of memory modules, at least one of the memory modules having physical characteristics different than other of said plurality of memory modules, a single built-in self test WISP controller that stores a set of commands defining an algorithm for testing the plurality of memory modules; a plurality of sequencers, each sequencer associated with a respective set of one or more memory modules that share common physical characteristics and operative to receive the commands and issue one or more memory operations in accordance with the commands; and a plurality of memory interfaces, each memory interface operative to apply the memory operations to an associated memory module in accordance with physical characteristics of the memory module, wherein the BIST controller comprises: an algorithm memory that stores the set of commands as one of a set of selectable memory test algorithms having associated commands; and an algorithm controller to retrieve the commands from the algorithm memory and issue the commands associated with the selected memory test algorithm to the sequencer, wherein the algorithm controller issues each of the commands to the sequencers in parallel for application to the respective subsets of the memory interfaces.

21. The system of claim 20, wherein the BIST controller includes an interface to receive one or more additional memory test algorithms, wherein the algorithm controller delivers the additional memory test algorithm to the sequencer for application to the memory interface.

22. The system of claim 20, further comprising a set of command data interconnects to communicate the commands from the BIST controller to the plurality of sequencers and a set of acknowledgement interconnects to communicate acknowledge signals from the plurality of sequencers to the BIST controller to indicate the completion of the commands.

Description Submit all comments and votes

TECHNICAL FIELD

The disclosure relates to electronic devices and, in particular, built-in self-test architectures for use in electronic devices.

BACKGROUND

Built-in self-test (BIST) units are now commonly incorporated into memory chips and other integrated circuits to test their functionality and reliability. For example, a BIST unit incorporated into a particular memory module operates by writing and reading various data patterns to and from the associated memory module to detect any possible memory faults. By comparing the data written and the data subsequently returned from the memory module, the BIST unit is able to determine whether any memory cell of the memory module is faulty.

The integrated BIST unit typically generates a variety of predetermined test patterns and asserts or deasserts an output signal based on the results of the memory test. A variety of algorithms may be used for detecting memory faults. For example, test patterns of all zeros, all ones, or a "checkerboard" pattern having alternating zeros and ones may be written throughout the memory cells. Moreover, the data may be written to the cells in any order, such as consecutively in an increasing or decreasing addressing scheme.

Thus, BIST units are commonly included in many types of integrated circuits that use or otherwise incorporate memory modules and operate according to some predetermined algorithm to verify the functionality of the internal chip circuitry. However, electronic devices typically comprise more than the internal circuitry of a single chip. Normally they are constructed from many integrated circuit chips and many supporting components mounted on a circuit board.

As the complexity of a typical computing device increases, the number of memory chips and other integrated circuits increases. For example, conventional computing devices typically include a plurality of the memory modules, which are often of different types. The memory modules within a single computing device may include various combinations of random access memory (RAM), read-only memory (ROM), Flash memory, dynamic random access memory (DRAM), and the like. These various types of memory modules often require different testing procedures, and have different bit densities, access speeds, addressing requirements, access protocols, and other particularities. As a result, a typical computing device may have a respective BIST unit for each memory module, and each BIST unit may be particularized to test the associated memory module.

SUMMARY

In general, the disclosure is directed to a distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules.

The BIST controller provides centralized, high-level control over the testing of the memory modules. The BIST controller communicates centrally stored and maintained test algorithms to the sequencers for application to the memory modules. The BIST controller communicates the algorithms as a set of generalized commands that conform to a command protocol described herein. Moreover, the command protocol allows algorithms to be generically defined without regard to any timing requirements, physical organization or particular interface characteristics of the memory modules. As a result, a variety of test algorithms may easily be defined and centrally-maintained for distribution throughout an electronic device as needed. Consequently, common test patterns need not be redundantly stored within memory modules.

The sequencers provide a second level of abstraction. The sequencers are distributed within device blocks that include one or more memory modules. In this manner, each sequencer is associated with one or more memory modules. The sequencers receive the high-level commands from BIST controller. In response to the commands, the sequencers issue a sequence of one or more memory operations to their respective memory interfaces to carry out the commands. For example, a sequencer may issue commands to sequentially access a range of addresses in response to a single command from the BIST controller. The sequencers report the results of the tests to the BIST controller.

The sequencers control the application of the operations in accordance with the timing characteristics of their respective memory modules. For example, each of the sequencers controls the application speed of the sequence of operations in accordance with the access speed of the respective memory module. A single sequencer may control the application of the test algorithms to a plurality of memory modules that operate on a common clock domain. Consequently, logic for controlling application timing and sequencing of the test pattern domain is incorporated within the sequencers, and need not be distributed within the individual memory modules or maintained by the BIST controller.

The third tier, the memory interfaces, handles specific interface requirements for each of the memory modules. Each of the memory interfaces may be designed in accordance with the particular signal interface requirements and physical characteristics of the respective one of memory modules. Each memory interface receives memory operations from a controlling sequencer, and translates the memory operations, including associated address and data signals, as needed based on the physical characteristics of the respective memory module. For example, a memory interface may translate addresses supplied by the controlling sequencer based on the rows and columns of the memory module to fill a memory in a row-wise or column-wise fashion. As another example, the memory interface may translate the data to create specific bit patterns, such as a checkerboard pattern or as "striped" rows or columns in which adjacent rows or columns have opposing patterns.

In one embodiment, a system comprises a built-in self-test (BIST) controller, a sequencer, and a memory interface coupled to a memory module. The BIST controller stores a set of commands defining an algorithm for testing the memory module. The sequencer receives the commands and issues one or more memory operations in accordance with the commands. The memory interface applies the memory operations to the memory module in accordance with physical characteristics of the memory module.

In another embodiment, a system comprises a plurality of memory modules, a built-in self-test (BIST) controller, and a plurality of sequencers. The BIST controller stores an algorithm for testing the memory modules. The plurality of sequencers are respectively coupled to different subsets of the memory modules, wherein each subset of the memory module is selected to include the memory modules having common clock domains. Each sequencer controls the application of the test algorithm to the respective subset of memory modules in accordance with the common clock domain of that subset of memory modules.

In another embodiment, a device comprises a first-level built-in, self-test (BIST) means for issuing commands that define a BIST algorithm for a plurality of distributed memory modules having different timing requirements and physical characteristics, and a second-level BIST means for processing the commands to generate sequences of memory operations in accordance with the timing requirements of the memory modules. The device further comprises a third-level BIST means for generating translated address and data signals from the memory operations based on the physical characteristics of the memory modules to apply the BIST algorithm to the distributed memory modules.

In another embodiment, a method comprises issuing commands from a centralized BIST controller to a sequencer, wherein the commands define a memory test algorithm to be applied to a set of distributed memory modules without regard to physical characteristics or timing requirements of the memory modules, and processing the commands with the sequencer to generate one or more sequences of memory operations in accordance with the timing requirements of the memory modules. The method further comprises applying the memory operations to the distributed memory modules to test the memory modules.

The techniques described herein may achieve one or more advantages. For example, the techniques may allow a variety of test algorithms to easily be defined and maintained centrally in the form of generalized commands. The generalized commands can be distributed to sequencers located throughout an electronic device for interpretation and application to memory modules. As a result, common test algorithms need not be redundantly stored within the memory modules.

In addition, the techniques may provide for the simultaneous application of algorithms to different memory modules, which may reduce overall test time and more thoroughly test for inter-memory effects. Moreover, the distributed, hierarchical nature of the architecture may allow the techniques to be readily applied to existing chip designs.

The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating an example electronic device having a distributed, hierarchical built-in self-test (BIST) architecture.

FIG. 2 is a block diagram illustrating an example embodiment of a BIST controller.

FIG. 3 is a timing diagram that further illustrates communication between the BIST controller and a set of sequencers for a single command of a generic BIST algorithm.

FIG. 4 is a block diagram illustrating an example embodiment of a device block.

FIG. 5 is a block diagram illustrating an example embodiment of a sequencer.

FIG. 6 is a block diagram illustrating an example embodiment of a memory interface.

FIG. 7 is a block diagram that illustrates an example embodiment of a data generation unit.

FIG. 8 is a block diagram illustrating an example data structure of a command issued by the BIST controller.

FIGS. 9A 9E illustrate exemplary data structures in accordance with the command protocol described herein.

FIG. 10 is a flowchart illustrating example operation of the distributed, three-tier self-test architecture.

DETAILED DESCRIPTION

FIG. 1 is a block diagram illustrating an example electronic device 2 having a distributed, hierarchical built-in self-test (BIST) architecture. In particular, electronic device 2 includes a built-in self-test (BIST) controller 4 that provides centralized, high-level control over testing of device blocks 6A through 6N (collectively "device blocks 6"). Each of device blocks 6 includes a sequencer 8, and a set of one or more memory interfaces 10 and one or more respective memory modules 12.

In general, BIST controller 4 provides and communicates test algorithms to sequencers 8 for application to device blocks 6. BIST controller 4 communicates each of the algorithms to sequencers 8 as a set of commands that conform to a generic and flexible command protocol. Each command specifies an operational code and a set of parameters that define one or more memory operations without regard to the physical characteristics or timing requirements of memory modules 12. In this manner the command protocol allows a variety of test algorithms to easily be defined and distributed throughout electronic device 2. Consequently, BIST controller 4 provides centralized control over the maintenance and distribution of the algorithms. As a result, common test algorithms need not be redundantly stored within device blocks 6.

Sequencers 8 interpret and execute the test algorithms provided by BIST controller 4. In particular, sequencers 8 receive high-level commands from BIST controller 4 that define a complete BIST algorithm. A single command, for example, may define a particular bit pattern to be written over a range of one or more addresses. In response to the commands, each of sequencers 8 issues one or more sequences of memory operations to their respective memory interfaces 10 to perform the commands. Moreover, sequencers 8 control the application of the operations in accordance with the timing characteristics of their respective memory modules 12. For example, each of sequencers 8 controls the application speed of the sequence of operations in accordance with the access speed of the respective memory module 12. A single sequencer 8, e.g., sequencer 8A, may control the application of the test algorithms to one or more memory modules, e.g., memory modules 12A, that operate on a common clock domain. Memory modules 12 may be grouped and assigned to respective sequencers 8 based on any of a variety of criteria, such as clock domains for each of the memory modules and any pre-existing hierarchy or grouping of the memory modules. Consequently, logic for controlling application timing and sequencing of the test pattern for memory modules 12 operating on a common clock domain may be incorporated within a common sequencer 8, and need not distributed within the individual memory modules.

Memory interfaces 10 handle specific interface requirements for each of memory modules 12. For example, each of memory interfaces 10 may be designed in accordance with the particular signal interface requirements and physical characteristics of the respective one of memory modules 12. As a result, each of memory interfaces 10 may be viewed as providing an interface "wrapper" around the particular interface signals, e.g., address, data, and control signals, for each respective memory module 12. In this manner, the BIST architecture of electronic device 2 comprises a three-tier, distributed arrangement including BIST controller 4, sequencers 8, and memory interfaces 10.

Memory modules 12 may be any type of memory, such as random access memory (RAM), read-only memory (ROM), Flash memory, dynamic random access memory (DRAM), SDRAM, RDRAM, DDR-RAM, combinations thereof, and the like, and the techniques described herein are not limited in this regard. Moreover, electronic device 2 may be any device that incorporates memory modules, such as an embedded computing system, a computer, server, personal digital assistant (PDA), mobile computing device, mobile communication device, digital recording device, network appliance, mobile positioning device, and the like.

FIG. 2 is a block diagram illustrating an example embodiment of BIST controller 4. In this illustrated embodiment, BIST controller 4 includes an algorithm memory 20 that stores a set of N test algorithms. As described below, each algorithm is defined in accordance with a set of binary commands. In one embodiment, for example, a complete algorithm may be specified by a set of 32-bit commands, where the commands define all necessary parameters for performing one or more sequences of memory operations over address ranges of device blocks 6 (FIG. 1) to test the functionality of memory modules 12.

User interface 22 invokes algorithm controller 26 in response to external input, such as a control signal from an external testing apparatus. Alternatively, algorithm controller may be automatically invoked upon power-up of electronic device 2. Once invoked, algorithm controller 26 provides an algorithm select signal (ALG_SELECT) to multiplexer 24 to select one of the algorithms stored within algorithm memory 20. Once selected, a stream of binary commands that comprises the selected algorithm is applied to device blocks 6 as command data (CMD_DATA).

Algorithm controller 26 controls the delivery of the algorithms to device blocks 6 based on acknowledge signals (SEQ_ACK) received from each sequencer 8 of the device blocks. In particular, algorithm controller 26 sequentially delivers each command of the selected algorithm to sequencers 8, and proceeds from one command to the next upon receiving an acknowledge signal from each of sequencers 8. In this manner, algorithm controller 26 ensures that each sequencer 8 has completed application of a current command to memory modules 12 via memory interfaces 10 before proceeding to the next command. Algorithm controller 26 may be programmatically or statically configured to establish the number of device blocks 6 and, in particular, sequencers 8 that are present within electronic device 2. In addition, algorithm controller 26 may be programmatically configured to apply a given algorithm to one, all, or any combination of memory modules 12 using any combination of device blocks 6.

In addition to the algorithms stored in algorithm memory 20, user interface 22 may programmably receive algorithms via external input. User interface 22 delivers the received algorithms to multiplexer 24 in a form similar to that of the stored algorithms, i.e., a sequence of binary commands in which each command defines a test within the overall algorithm. In this manner, BIST controller 4 provides a centralized, first tier of the three-tier, distributed self-test architecture.

FIG. 3 is a timing diagram that further illustrates communication between BIST controller 4 and sequencers 8 for a single command of a generic BIST algorithm. As illustrated, at a time T1, BIST controller 4 asserts the command request (CMD_REQ) interconnects, and communicates a current command of the algorithm on the CMD_DATA interconnects.

Upon receiving and applying the command, sequencers 8 assert a corresponding SEQ_ACK signal. For example, in the illustrated example, each of sequencers 8 assert respective signals SEQ_ACK[1], SEQ_ACK[2], SEQ_ACK[N] and SEQ_ACK[0] at times T2, T3, T4 and T5, respectively. In response, BIST controller 4 de-asserts the command request (CMD_REQ) signal at a time T6, causing sequencers 8 to de-assert their respective SEQ_ACK signal. BIST controller 4 asserts SEQS_DONE signal when all SEQ_ACK signals have been de-asserted, allowing BIST controller 4 to initiate another command at a time T7.

FIG. 4 is a block diagram illustrating an example embodiment of a device block, e.g., device block 6A, in more detail. As illustrated, device block 6A includes sequencer 8A, a set of memory interfaces 10A 10C (collectively "memory interfaces 10"), and a set of memory modules 12A 12C (collectively "memory modules 12"). As illustrated in FIG. 4, each of memory interfaces 10 corresponds to a respective memory module 12. Sequencer 8A may be programmatically and/or statically configured to establish the number of memory interfaces 10 to be controlled, as well as the characteristics, e.g., maximum address, for the largest of memory modules 12.

FIG. 5 is a block diagram illustrating an example embodiment of a sequencer, e.g., sequencer 8A, in more detail. Sequencer 8A receives high-level commands from BIST controller 4 that collectively define a BIST algorithm. As illustrated in detail below, BIST controller 4 issues the commands in a generic, flexible format, and a single command may define a particular bit pattern to be written over a range of one or more addresses.

In general, sequencer 8A receives the generic BIST commands, and controls the application of each command as a sequence of one or more memory operations applied to a set of respective memory modules. In the illustrated embodiment, sequencer 8A includes a command parser (CMD PARSER) 30 that receives command data (CMD_DATA) from BIST controller 4. Command parser 30 processes the received command to identify the specified operation, e.g., by identifying an operational code (op-code) specified by the command.

Based on the specified operation, command parser 30 may extract one or more parameters from the command, and select a corresponding one of command controllers (CMD CONTROLLER) 34A 34N. In other words, each one of command controllers 34 corresponds to a different command that may be specified by CMD_DATA. Command parser 30 invokes the selected command controller 34, and passes the parameters extracted from the received command. Although illustrated separately, command controllers 34 may be combined and/or integrated into a single functional block having logic to perform each of the supported commands.

In response to each command, the invoked one of command controllers 34 issues a sequence of one or more operations to each memory interface 10. In particular, the invoked one of command controllers 34 sequentially drives the appropriate command control signals (CMD_CTRL_SIGNALS) to carry out each operation of the sequence. The command control signals may include signals to provide a memory address and data to the receiving memory interfaces 10 and to direct the receiving memory interfaces to invert bits, perform read or write operations, invert rows, and the like, as further described below.

Moreover, command controller 34 controls the application of the operations in accordance with the timing characteristics of their respective memory modules 12. Consequently, logic for controlling application timing and sequencing of the operations for memory modules 12 operating on a common clock domain may be incorporated within a common sequencer 8, and need not distributed within the individual memory modules.

Sequencer 8A receives data from the tested memory modules 12, e.g., via signals MEM[0]_DOUT throughout MEM[N]_DOUT, and selectively communicates the data back to BIST controller 4 or an external device via multiplexer 37 and data selection signal 39. In this manner, sequencers 8 allow for the analysis of the data to identify any failures.

Thus, sequencers 8 allow BIST controller 4 to centrally manage the storage and issuance of algorithms using generic and flexible command format. Sequencers 8 receive the generic BIST commands in accordance with the command protocol, and control the application of the commands by generating and issuing sequences of one or more memory operations for application to a set of respective memory modules 12, thereby providing a second tier of the distributed, hierarchical self-test architecture.

FIG. 6 is a block diagram illustrating an example embodiment of a memory interface 41 that provides the final layer of abstraction of the distributed BIST architecture by handling specific interface requirements for a respective memory module 12.

In the illustrated embodiment, memory interface 41 includes a layer