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Preventive treatment method for a multilayer semiconductor wafer
   
Document Number
US Patent 7190029
Issued Date
March 13, 2007
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Abstract
A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatment.
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Number of Claims:
11
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Published
March 13, 2007
Application Number
11/157,956
Filed
June 22, 2005
US Classification
257/347   257/E21.568
Int'l Classification
H01L   27/12   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a division of application Ser. No. 10/784,040 filed Feb. 20, 2004, now U.S. Pat. No. 6,939,783 which claims the benefit of application Ser. No. 60/483,477 filed Jun. 26, 2003, the entire content of each of which is expressly incorporated herein by reference.
Priority Data
Mar 04, 2003 [FR] 03 02623
USPTO Field of Search
257/347  
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