A laminated capacitor includes a capacitor body and first, second, third and fourth external electrodes disposed on an external surface of the capacitor body. The capacitor body has first and second electrode patterns that are alternately laminated with dielectric layers between. The first electrode pattern provides a first internal electrode that is connected to both the first and second external electrodes. The second electrode pattern provides second and third internal electrodes. The second internal electrode is connected to both the third and fourth external electrodes. The third internal electrode is disposed in the same layer as the second internal electrode and connected to one of the third and fourth external electrodes.
A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.
