The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.
RELATED APPLICATIONS
This application claims priority to and the benefit of: earlier filed U.S. Provisional Application Ser. No. 60/468,438, filed May 7, 2003, entitled "Multi-Channel CMOS formatter;" earlier filed U.S. Provisional Application Ser. No. 60/505,912, filed Sep. 25, 2003, entitled "Test Systems and Methods;" and earlier filed U.S. Provisional Application Ser. No. 60/506,986, filed Sep. 29, 2003, entitled "Test Systems and Methods;"
