A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.
An interrupt controller superior in maintenance performance and expandability. An interrupt controller 10 comprises a queue circuit 11 that holds channel numbers corresponding to interrupt inputs in the order of priority levels, and a queue control circuit 12 that changes the order of the channels held in the queue circuit 11 according to a new order of the priority levels when a priority level that corresponds to any channel number is changed. The order of the channel numbers in the queue circuit 11 is changed at a time of setting the priority levels unrelated to interrupt inputs. In order to select an interrupt to be notified to a CPU 20, an interrupt factor selection circuit 15 checks whether or not each channel number held in the queue circuit 11 has an interrupt input in turn from the head of the queue.
