A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.
