An image pickup element and a micro-lens part are formed on the front surface of a semiconductor substrate; through electrodes passing through the semiconductor substrate are formed; protruding parts protruding from the front surface toward a glass lid are formed in a thickness greater than the thickness of the micro-lens part on the through electrodes; and the protruding parts are interposed between the semiconductor substrate and the glass lid.
A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to the pads; the via holes penetrate the chip and are electrically connected to the pad extension traces and exposed out of side surfaces of the semiconductor package structure; the lid is adhered onto the active surface of the chip; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.
The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer. According to the present invention, it is possible to realize a cheap wafer level chip size package (WL-CSP) using the existing wafer processing and the metal deposition processing equipments. Further, an image sensor module with smaller thickness and area than the existing CSP package can be realized. Moreover, an image sensor module with a smaller area than the existing COG package can be realized.
Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.
