Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices
A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may then access the table in order to determine the transmission mode, broadcast or point-to-point, which corresponds to the received transaction.
This application is a continuation-in-part of U.S. patent application Ser. No. 10/136,619, filed May 1, 2002, now U.S. Pat. No. 7,032,078. This application also claims the benefit of U.S. provisional patent application Ser. No. 60/392,179, filed Jun. 28, 2002.
Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the upper limit of the performance of the multi-processor system from deteriorating (prevent latency from increasing). An address snoop method for a multi-processor system having a structure in which a plurality of processor blocks each having a plurality of processors and a plurality of memories are coupled to a plurality of input and output (I/O) blocks via an address connecting apparatus, is configured to carry out an address snoop process that judges whether to respond with respect to an access request, in the address connecting apparatus in place of each I/O block, when the access request is generated from an arbitrary one of the processor blocks.
Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
