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Enabling and disabling cache bypass using predicted cache line usage
 
   
Document Number
US Patent 7228388
Issued Date
June 5, 2007
Link
Inventors
Hu; Zhigang (Ossinging, NY)
Robinson; John T. (Yorktown Heights, NY)
Shen; Xiaowei (Hopewell Junction, NY)
Sinharoy; Balaram (Poughkeepsie, NY)
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Abstract
Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed. Included is an arrangement for selectively enabling or disabling cache bypass with respect to at least one cache line based on historical cache access information.
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Number of Claims:
21
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Published
June 5, 2007
Application Number
10/993,531
Filed
November 19, 2004
US Classification
711/138   711/122 711/E12.021 711/E12.043
Int'l Classification
G06F   12/00   (20060101)  
Examiner
USPTO Field of Search
711/118   711/122   711/138  
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