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Built-in self-test (BIST) for high performance circuits
 
   
Document Number
US Patent 7228478
Issued Date
June 5, 2007
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Abstract
Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that enable the MUX to select appropriate input signals. The circuit arrangement enables relatively few seed patterns to generate relatively large number of test patterns. The seed patterns are a sub-set of a test pattern set preferably generated by software such as the Automatic Test Pattern Generator (ATPG). A method to generate the seed patterns is, also, provided.
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Number of Claims:
15
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Published
June 5, 2007
Application Number
10/915,981
Filed
August 11, 2004
US Classification
714/738   714/735
Int'l Classification
G01R   31/3183   (20060101)   G01R   31/3185   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
714/738   714/741   714/735   714/733   714/732   714/728   714/25   714/30  
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